- 24 Jul, 2019 5 commits
-
-
Julius Werner authored
The Rockchip platform is a prime candidate for switching to the new bl31_params_parse_helper(), so switch it over. This will allow BL2 implementations on this platform to transparently switch over to the version 2 parameter structure. Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
BL31 used to take a single bl31_params_t parameter structure with entry point information in arg0. In commit 72600226 (Add new version of image loading.) this API was changed to a more flexible linked list approach, and the old parameter structure was copied into all platforms that still used the old format. This duplicated code unnecessarily among all these platforms. This patch adds a helper function that platforms can optionally link to outsource the task of interpreting arg0. Many platforms are just interested in the BL32 and BL33 entry point information anyway. Since some platforms still need to support the old version 1 parameters, the helper will support both formats when ERROR_DEPRECATED == 0. This allows those platforms to drop a bunch of boilerplate code and asynchronously update their BL2 implementation to the newer format. Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
This patch adds a new include/export/ directory meant for inclusion in third-party code. This is useful for cases where third-party code needs to interact with TF-A interfaces and data structures (such as a custom BL2-implementation like coreboot handing off to BL31). Directly including headers from the TF-A repository avoids having to duplicate all these definitions (and risk them going stale), but with the current header structure this is not possible because handoff API definitions are too deeply intertwined with other TF code/headers and chain-include other headers that will not be available in the other environment. The new approach aims to solve this by separating only the parts that are really needed into these special headers that are self-contained and will not chain-include other (non-export) headers. TF-A code should never include them directly but should instead always include the respective wrapper header, which will include the required prerequisites (like <stdint.h>) before including the export header. Third-party code can include the export headers via its own wrappers that make sure the necessary definitions are available in whatever way that environment can provide them. Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
It's not a good idea to use u_register_t for the members of aapcs64_params_t and aapcs32_params_t, since the width of that type always depends on the current execution environment. This would cause problems if e.g. we used this structure to set up the entry point of an AArch32 program from within an AArch64 program. (It doesn't seem like any code is doing that today, but it's probably still a good idea to write this defensively. Also, it helps with my next patch.) Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
This patch changes all Rockchip platforms to use the new common BL aux parameter helpers. Since the parameter space is now cleanly split in generic and vendor-specific parameters and the COREBOOT_TABLE parameter is now generic, the parameter type number for that parameter has to change. Since it only affects coreboot which always builds TF as a submodule and includes its headers directly to get these constants, this should not cause any issues. In general, after this point, we should avoid changing already assigned parameter type numbers whenever possible. Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 18 Jul, 2019 1 commit
-
-
Julius Werner authored
This patch adds some common helper code to support a lightweight platform parameter passing framework between BLs that has already been used on Rockchip platforms but is more widely useful to others as well. It can be used as an implementation for the SoC firmware configuration file mentioned in the docs, and is primarily intended for platforms that only require a handful of values to be passed and want to get by without a libfdt dependency. Parameters are stored in a linked list and the parameter space is split in generic and vendor-specific parameter types. Generic types will be handled by this code whereas vendor-specific types have to be handled by a vendor-specific handler function that gets passed in. Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 16 Jul, 2019 1 commit
-
-
Soby Mathew authored
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
-
- 15 Jul, 2019 1 commit
-
-
Soby Mathew authored
-
- 12 Jul, 2019 18 commits
-
-
Madhukar Pappireddy authored
Fix the header file path Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
-
Sandrine Bailleux authored
* changes: rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4 rcar_gen3: drivers: rpc: Modify PFC code rcar_gen3: drivers: rpc: Change RPC PHY calibration setting rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: ddr-a: Update E3 DDR setting
-
Sandrine Bailleux authored
-
Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I94acd1bb53d9d2453e550e2a13b6391b9088ff8d
-
Toshiyuki Ogasahara authored
Modify PFC code and rename macro of MFIS according to Errata of Hardware User's Manual Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac
-
Toshiyuki Ogasahara authored
Modify RPC code according to Errata of Hardware User's Manual Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I82d0a2136c7f18870842f84c49343977708eef1e
-
Chiaki Fujii authored
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.36. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ia4fc9456876a14a9cf3ced93163477974f6cc8bf
-
John Tsichritzis authored
As it turns out, Gerrit's merge commits don't always respect that format so these mistakes have to be ignored as false positives. Change-Id: I4e38d9c34c95588e7916fba4c154f017d8c92dec Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
Sandrine Bailleux authored
-
Justin Chadwell authored
The -Wshift-overflow=2 option enables checks for left bit shifts. Specifically, the option will warn when the result of a shift will be placed into a signed integer and overflow the sign bit there, which results in undefined behavior. To avoid the warnings from these checks, the left operand of a shift can be made an unsigned integer by using the U() macro or appending the u suffix. Change-Id: I50c67bedab86a9fdb6c87cfdc3e784f01a22d560 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I67984b6c48c08af61e95a4dbd18047e2c3151f9a Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I54560fe290e7dc52d364d0fe1c81a16f4c8d9a7b Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Sandrine Bailleux authored
-
Sandrine Bailleux authored
-
Hiroyuki Nakano authored
[IPL/DDR] - Update E3 DDR setting rev.0.12. Signed-off-by: Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc
-
- 11 Jul, 2019 11 commits
-
-
John Tsichritzis authored
-
John Tsichritzis authored
-
John Tsichritzis authored
Merge "driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms" into integration
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib63ef6e2e4616dd56828bfd3800d5fe2df109934 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I51278beacbe6da79853c3f0f0f94cd806fc9652c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7ec8ed3423e9b9b32be2388520bc27ee28f6370 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
-
Tien Hock, Loh authored
Designware MMC DMA FIFO threshold shouldn't be changed as it broke Poplar platform's uboot MMC Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I87ec9d5a78e1bf45119cb73797e402b25a914c13
-
John Tsichritzis authored
-
- 10 Jul, 2019 3 commits
-
-
Alexei Fedorov authored
This patch adds 128-bit integer types int128_t and uint128_t for "__int128" and "unsigned __int128" supported by GCC and Clang for AArch64. Change-Id: I0e646d026a5c12a09fd2c71dc502082052256a94 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
Alexei Fedorov authored
This patch removes incorrect SCTLR_V_BIT definition and adds definitions for ARMv8.3-Pauth EnIB, EnDA and EnDB bits. Change-Id: I1384c0a01f56f3d945833464a827036252c75c2e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
Balint Dobszay authored
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
-