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Most DTBs used on the RaspberryPi contain a FDT /memreserve/ region,
that covers the original secondaries' spin table.
We need to reserve more memory than described there, to cover the whole
of the TF-A image, so we add a /reserved-memory node to the DTB.

However having the same memory region described by both methods upsets
the Linux kernel and U-Boot, so we have to make sure there is only one
instance describing this reserved memory.

Keep our currently used /reserved-memory node, since it's more capable
(it allows to mark the region as secure memory). Add some code to drop
the original /memreserve/ region, since we don't need this anymore,
because we take the secondaries out of their original spin loop.

We explicitly check for the currently used size of 4KB for this region,
to be alerted by any changes to this region in the upstream DTB.

Change-Id: Ia3105560deb3f939e026f6ed715a9bbe68b56230
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Bumps [path-parse](https://github.com/jbgutierrez/path-parse) from
1.0.6 to 1.0.7.

- [Release notes](https://github.com/jbgutierrez/path-parse/releases)
- [Commits](https://github.com/jbgutierrez/path-parse/commits/v1.0.7

)

---
updated-dependencies:
- dependency-name: path-parse
  dependency-type: indirect
...

Change-Id: Ic51c94f3c90d4eab91aeb3b477622358bf74c636
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: dependabot[bot] <support@github.com>

* changes:
  feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
  feat(plat/rcar3): add a DRAM size setting for M3N
  feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
  feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
  feat(drivers/rcar3): ddr: add function to judge a DDR rank
  fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
  fix(drivers/rcar3): i2c_dvfs: fix I2C operation
  fix(drivers/rcar3): fix CPG registers redefinition
  fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
  fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
  refactor(plat/rcar3): factor out DT memory node generation
  feat(plat/rcar3): add optional support for gzip-compressed BL33

* changes:
  feat(io_mtd): offset management for FIP usage
  feat(nand): count bad blocks before a given offset
  feat(plat/st): add helper to save boot interface
  fix(plat/st): improve DDR get size function
  refactor(plat/st): map DDR secure at boot
  refactor(plat/st): rework TZC400 configuration

This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd

Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, and it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe

Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, but the workaround only applies to r1p0 and r1p1, it is still
open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b

This reverts commit 4d9b9b23

.

Timeout in IPI ack was added for functional safety reason.
Functional safety is not criteria for ATF. However, this
creates issues for APIs that take long or non-deterministic
duration like FPGA load. So revert this patch for now to fix
FPGA loading issue. Need to add support for non-blocking API
for FPGA loading with callback when API completes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6

DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9c7af9a4f75216ed2c6b44458d121a352bef4b95

Fixed the build error by removing the local definition of 'efi_guid'
structure in 'sgi_ras.c' file as this structure definition is already
populated in 'sgi_ras.c' file via 'uuid.h' header.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I57687336863f2a0761c09b6c1aa00b4aa82a6a12

Bump the required FF-A version in framework and manifests to v1.1 as
upstream feature development goes.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I89b2bd3828a13fc4344ccd53bc3ac9c0c22ab29f

Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52

Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe

Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123

NXP drivers header files are moved:
  - from:  drivers/nxp/<xx>/*.h
  - to  :  include/drivers/nxp/<xx>/*.h

To accommodate these changes each drivers makefiles
drivers/nxp/<xx>/xx.mk, are updated.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21

* changes:
  feat(sw_crc32): add software CRC32 support
  refactor(hw_crc32): renamed hw_crc32 to tf_crc32
  feat(fwu): avoid booting with an alternate boot source
  docs(fwu): add firmware update documentation
  feat(fwu): avoid NV counter upgrade in trial run state
  feat(plat/arm): add FWU support in Arm platforms
  feat(fwu): initialize FWU driver in BL2
  feat(fwu): add FWU driver
  feat(fwu): introduce FWU platform-specific functions declarations
  docs(fwu_metadata): add FWU metadata build options
  feat(fwu_metadata): add FWU metadata header and build options

Added software CRC32 support in case platform doesn't support
hardware CRC32.

Platform must include necessary Zlib source files for compilation
to use software CRC32 implementation.

Change-Id: Iecb649b2edf951944b1a7e4c250c40fe7a3bde25
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Renamed hw_crc32 to tf_crc32 to make the file and function
name more generic so that the same name can be used in upcoming
software CRC32 implementation.

Change-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

All firmware banks should be part of the same non-volatile storage
as per PSA FWU specification, hence avoid checking for any alternate
boot source when PSA FWU is enabled.

Change-Id: I5b016e59e87f1cbfc73f4cd29fce6017c24f88b3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
   and updated components in I/O policy

Change-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Avoided NV counter update when the system is running in
trial run state.

Change-Id: I5da6a6760f8a9faff777f2ff879156e9c3c76726
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Added firmware update support in Arm platforms by using
FWU platform hooks and compiling FWU driver in BL2
component.

Change-Id: I71af06c09d95c2c58e3fd766c4a61c5652637151
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Initialized FWU driver module in BL2 component under
build flag PSA_FWU_SUPPORT.

Change-Id: I08b191599835925c355981d695667828561b9a21
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Implemented FWU metadata load and verification APIs.
Also, exported below APIs to the platform:
1. fwu_init - Load FWU metadata in a structure. Also, set the
	      addresses of updated components in I/O policy
2. fwu_is_trial_run_state - To detect trial run or regular run
			    state

Change-Id: I67eeabb52d9275ac83be635306997b7c353727cd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Added FWU platform specific functions declarations in common
platform header.

Change-Id: I637e61753ea3dc7f7e7f3159ae1b43ab6780aef2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>