- 22 Jul, 2019 1 commit
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Imre Kis authored
The AArch32 system registers are not listed if the platform supports AArch64 only. Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679 Signed-off-by:Imre Kis <imre.kis@arm.com>
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- 17 Jul, 2019 7 commits
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Soby Mathew authored
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Louis Mayencourt authored
When pointer authentication is enabled, the LR value saved on the stack contains a Pointer Authentication Code (PAC). It must be stripped to retrieve the return address. The PAC field is stored on the high bits of the address and defined as: - PAC field = Xn[54:bottom_PAC_bit], when address tagging is used. - PAC field = Xn[63:56, 54:bottom_PAC_bit], without address tagging. With bottom_PAC_bit = 64 - TCR_ELx.TnSZ Change-Id: I21d804e58200dfeca1da4c2554690bed5d191936 Signed-off-by:Louis Mayencourt <louis.mayencourt@arm.com>
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Soby Mathew authored
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Soby Mathew authored
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Soby Mathew authored
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Soby Mathew authored
* changes: rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style rcar_gen3: drivers: ddr-a: Pass ddrBackup around rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32() rcar_gen3: drivers: ddr-a: Unify register definitions -
Soby Mathew authored
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- 16 Jul, 2019 3 commits
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Usama Arif authored
This patch adds support for Cortex-A5 FVP for the DesignStart program. DesignStart aims at providing low cost and fast access to Arm IP. Currently with this patch only the primary CPU is booted and the rest of them wait for an interrupt. Signed-off-by:Usama Arif <usama.arif@arm.com> Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
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Ambroise Vincent authored
Update the skeleton implementation of the console interface. The 32 bit version was outdated and has been copied from the 64 bit version. Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe Signed-off-by:Ambroise Vincent <ambroise.vincent@arm.com>
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Soby Mathew authored
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
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- 15 Jul, 2019 2 commits
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Soby Mathew authored
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Marek Vasut authored
Coding style cleanup, no functional change. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I689418768e87a8c1b6eeeb9f1a48dfb333908017
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- 14 Jul, 2019 7 commits
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Marek Vasut authored
Pass the ddrBackup variable around instead of making it a global variable. Signed-off-by: -
Marek Vasut authored
Partly inline ddr_init_e3.h into ddr_init_e3.c . Drop duplicate INITDRAM_* macros, which are defined in boot_init_dram.h . Signed-off-by: -
Marek Vasut authored
Coding style cleanup, no functional change. Signed-off-by: -
Marek Vasut authored
Coding style cleanup, no functional change. Signed-off-by: -
Marek Vasut authored
Replace ad-hoc register accessors with generic ones, remove the ad-hoc implementation. No functional change. Signed-off-by: -
Marek Vasut authored
Unify boot_init_dram_regdef_*.h into boot_init_dram_regdef.h and clean up it's coding style a bit. Signed-off-by: -
Marek Vasut authored
Remove the ad-hoc BITn macros and replace them with generic BIT(n) macro. No functional change. Signed-off-by:
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- 12 Jul, 2019 19 commits
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Madhukar Pappireddy authored
Fix the header file path Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
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Paul Beesley authored
Currently we have some pre-rendered versions of certain diagrams in SVG format. These diagrams have corresponding PlantUML source that can be rendered automatically as part of the documentation build, removing the need for any intermediate files. This patch adds the Sphinx "plantuml" extension, replaces references to the pre-rendered SVG files within the documents, and finally removes the SVG files and helper script. New requirements for building the docs are the "sphinxcontrib-plantuml" Python module (added to the pip requirements.txt file) and the Graphviz package (provides the "dot" binary) which is in the Ubuntu package repositories. Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d Signed-off-by:Paul Beesley <paul.beesley@arm.com>
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Sandrine Bailleux authored
* changes: rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4 rcar_gen3: drivers: rpc: Modify PFC code rcar_gen3: drivers: rpc: Change RPC PHY calibration setting rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: ddr-a: Update E3 DDR setting
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Sandrine Bailleux authored
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by:
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by:
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by:
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Toshiyuki Ogasahara authored
Modify PFC code and rename macro of MFIS according to Errata of Hardware User's Manual Signed-off-by:
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Toshiyuki Ogasahara authored
Modify RPC code according to Errata of Hardware User's Manual Signed-off-by:
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Chiaki Fujii authored
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.36. Signed-off-by:
Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by:
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John Tsichritzis authored
As it turns out, Gerrit's merge commits don't always respect that format so these mistakes have to be ignored as false positives. Change-Id: I4e38d9c34c95588e7916fba4c154f017d8c92dec Signed-off-by:John Tsichritzis <john.tsichritzis@arm.com>
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Sandrine Bailleux authored
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Justin Chadwell authored
The -Wshift-overflow=2 option enables checks for left bit shifts. Specifically, the option will warn when the result of a shift will be placed into a signed integer and overflow the sign bit there, which results in undefined behavior. To avoid the warnings from these checks, the left operand of a shift can be made an unsigned integer by using the U() macro or appending the u suffix. Change-Id: I50c67bedab86a9fdb6c87cfdc3e784f01a22d560 Signed-off-by:Justin Chadwell <justin.chadwell@arm.com>
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e Signed-off-by: -
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I67984b6c48c08af61e95a4dbd18047e2c3151f9a Signed-off-by: -
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I54560fe290e7dc52d364d0fe1c81a16f4c8d9a7b Signed-off-by: -
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: -
Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632 Signed-off-by: -
Sandrine Bailleux authored
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Sandrine Bailleux authored
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Hiroyuki Nakano authored
[IPL/DDR] - Update E3 DDR setting rev.0.12. Signed-off-by:
Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com> Signed-off-by:
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- 11 Jul, 2019 1 commit
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John Tsichritzis authored
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