- 27 Mar, 2017 1 commit
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Summer Qin authored
This patch modifies some of the functions in ARM platform layer to cater for the case when multi-threading `MT` is set in MPIDR. A new build flag `ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR now assume that the `MT` bit is set for the platform and access the bit fields accordingly. Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is enabled, returning the PE count within the physical cpu corresponding to `mpidr`. Change-Id: I04ccf212ac3054a60882761f4087bae299af13cb Signed-off-by: Summer Qin <summer.qin@arm.com>
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- 27 Feb, 2017 2 commits
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davidcunado-arm authored
RK3399 ARM TF clean up 20170210
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davidcunado-arm authored
Tegra changes from downstream v2
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- 24 Feb, 2017 30 commits
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Xing Zheng authored
Sorry to miss the security configuration for SRAM, if we don't support it, somebody may modify the comment of SRAM in the non-secure space. Let's fix this issue. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Derek Basehore authored
This fixes code that set a tFC value in a register using the tRFC value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Xing Zheng authored
On resume, we use the DFS hardware to switch frequency index, followed by a full training sequence on that index. Leaving the DFS training modules enabled causes issues with the full training done at resume. We also only needs these enabled during a call to ddr_set_rate during runtime, so there's no issue disabling them at the end of ddr_set_rate. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Derek Basehore authored
This moves the setting of the DQS drive strength to the M0 to minimize the impact on DDR transactions. We need to have the DQS drive strength changed for data training, which is triggered by the M0, but it also needs to be changed back when data training is finished. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This removes an optimization to not recalculate parameters if the frequency index being switched to hold the next frequency. This is because some registers do not have a copy per frequency index, so this optimization might be causing problems. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
We were getting far off values on resume for the RX_CAL_DQS values. This saves and restores the values for suspend/resume until the root of the problem is figured out Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Julius Werner authored
These macros were accidentally deleted in a previous cleanup. This slipped through because the code using them is currently unused, but that may change in the future. Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
This patch shuffles the M0 Makefile flags around a bit trying to make their purpose clearer and remove duplication. Since all three build steps (compiling, assembling, linking) actually call GCC, remove the misleading aliases $(AS) and $(LD) to avoid confusion that those tools might be called directly. Split flags into a common group that has meaning for all three steps and separate variables specific to each step. Remove -nostartfiles which is a strict subset of -nostdlib. Also add explicit parameters for -mfloat-abi=soft, -fomit-frame-pointer and -fno-common. If omitted these settings depend on the toolchain's built-in default and cause various problems if they resolve to unexpected values. Signed-off-by: Julius Werner <jwerner@chromium.org>
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Xing Zheng authored
The goal is that make clear the secure and SoC codes. Now cleaning them will help secure code extensions for RK3399 in the future. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Xing Zheng authored
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don't have to hardcode the range in two places. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Xing Zheng authored
Move the BL31 loaded base address 0x10000 to 0x1000, and configure the the memory range 0~1MB is secure, the goal is that make sure the BL31 image will be not modified. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Xing Zheng authored
So far, there are more and more features are supported on the RK3399, meanwhile, these features are increasingly being defined and intertwined. It's time to clean up and make them clearer. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Derek Basehore authored
This removes waiting for vblank on the M0 during ddrfreq transitions. That will now be done in the kernel to allow scheduling to be done on the CPU core that changes the ddr frequency. Waiting for vblank in the M0 would have the CPU core that waits on the M0 spin looping for up to 16ms (1 frame for the display). Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
we will set PMU_CRU_GATEDIS_CON0 when idle port, it will enable all clock, for save power consumption, we need to restore old value when finish it. Signed-off-by: Lin Huang <hl@rock-chips.com>
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Lin Huang authored
As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1 register, it need set the write_mask bit (bit16 ~ bit31), but as we test, it not need it. So need to correct the setting way, otherwise it will set wrong value to this register. Signed-off-by: Lin Huang <hl@rock-chips.com>
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Xing Zheng authored
We found that the DUT will be hanged if we don't set the bit_1 of the PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1 is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the TRM incorrect? We need to check it with the IC team and re-clean the commit message and explain it tomorrow. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Lin Huang authored
This patch do following things: 1. Request hresetn_cm0s_pmu_req first then request poresetn_cm0s_pmu_req during M0 enable. 2. Do not diable M0 clock for ddr dvfs. 3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1 4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate to the M0 clock. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
When vop is disabled and we read the vop register the system will hang, so check vop status when we wait for the DMA finish flag to avoid this sitiuation. This is done by checking for standby, DMA stop mode, and disabled window states. Any one of these will prevent the DMA finish flag from triggering. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
There is system timer in m0, we can use it to implement a set of stopwatch functions for measuring timeouts. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
The phy pll needs to get 2X frequency to the DDR, so set the pll_postdiv to 0. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Lin Huang authored
For ddr dfs stable, We need to enable ddr CA training when do ddr dfs. Signed-off-by: Lin Huang <hl@rock-chips.com>
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Derek Basehore authored
This fixes a hang with setting the DRAM rate based on a race condition with the M0 which sets the DRAM rate. The AP can also starve the M0, so this also delays the AP reads to the DONE parameter for the M0. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This enables per CS training at 666MHz and above for ddrfreq per vendor recommendation. Since the threshold was used for latency was the same value, this also adds a new value for that. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Derek Basehore authored
This patch sets the frequency configuration of the next DRAM DFS index to the configuration of the current index. This does not perform a frequency transition. It just configures registers so the training on resume for both indices will be correct. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Xing Zheng authored
We used dcf do ddr frequency scaling, but we just include a dcf binary, it hard to maintain later, we have M0 compile flow in ATF, and M0 can also work for ddr frequency scaling, so let's use it. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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Derek Basehore authored
This makes the file consistently use tabs instead of mixing in spaces. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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Xing Zheng authored
Since the ATF project, we usually use the mmio_read_32 and mmio_write_32. And the mmio_write_32, the firse parameter is ADDR, the second is VALUE. In order to style consistency: 1/ rename readl/writel to mmio_read_32/mmio_write_32 2/ for keeping the same with mmio_write_32 in the ATF project, swap the order of the parameters for M0 mmio_write_32 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Lin Huang <hl@rock-chips.com>
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Derek Basehore authored
when dram frequency below 260MHz, phy master dll may unlock, so let phy master dll working at dll bypass mode when frequency is below 260MHz. Signed-off-by: Lin Huang <hl@rock-chips.com>
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Derek Basehore authored
we can reuse the dram config from loader, so we can remove dram_init() and dts_timing_receive() funciton in dram.c, add the dram_set_odt_pd() function to get the odt and auto power down parameter from kernel. This also removes the dcf_code_init function to allow the system to actually boot. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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- 23 Feb, 2017 7 commits
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Varun Wadekar authored
This patch adds the pwr_domain_power_down_wfi() handler for Tegra platforms which in turn executes the soc specific `power_down_wfi` handler. Change-Id: I5deecc09959db3c3d73f928f5c871966331cfd95 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch maps the TZDRAM carveout used by the BL31. In the near future BL31 would be running from the TZRAM for security and performance reasons. The only downside to this solution is that the TZRAM loses its state in System Suspend. So, we map the TZDRAM carveout that the BL31 would use to save its state before entering System Suspend. Change-Id: Id5bda7e9864afd270cf86418c703fa61c2cb095f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch increases the BL31 image size for all Tegra platforms to 256KB, so that we can relocate BL31 to TZSRAM on supported chips. Change-Id: I467063c68632b53b5d4ef8ff1f76f5988096bd9c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch uses the Memory controller driver's handler to restore its settings and moves the other chip specific code to their own 'pwr_domain_on_finish' handlers. Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves the code to disable DCO operations out from common CPU files. This allows the platform code to call thsi API as and when required. There are certain CPU power down states which require the DCO to be kept ON and platforms can decide selectively now. Change-Id: Icb946fe2545a7d8c5903c420d1ee169c4921a2d1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the PSCI_EXTENDED_STATE_ID macro. Tegra platforms have moved on to using the extended state ID for CPU_SUSPEND, where the NS world passes the state ID and wakeup time as part of the state ID field. Change-Id: Ie8b0fec285d8b2330bc26ff239a4f628425c9fcf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform power states, PLAT_MAX_RET_STATE and PLAT_MAX_OFF_STATE, can change on Tegra SoCs and so should be defined per-soc. This patch moves these macro definitions to individual SoC's tegra_def.h files. Change-Id: Ib9b2752bc4d79cef6f79bee49882d340f71977a2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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